You will develop verification approaches, author and execute verification plans, and use formal analysis tools. While leading verification teams, you will define the test-bench architecture and verification approach. You will be responsible for developing methodologies and defining processes used by verification teams. You will also have the opportunity to lead multi-disciplinary teams and learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.
Duties and Responsibilities:
•Develop verification and test plans
•Develop UVM Agents for proprietary buses
•Instantiate VIPs for industry standard buses
•Work in both block-level/chip-level UVM testbench environment
•Work with RTL designers to resolve simulation issues
•Implement cover groups according to design requirements
•Work on code and functional coverage closures to achieve 100%
•Perform code reviews and to mentor junior engineers in the group
Required Qualifications:
•BS degree with 15 years' experience
•Fluent in System Verilog including SVA
•Recent experience with UVM/UVMF
•Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS)
•Familiarity with at least one IEEE bus standard
•Experience with DDR3/DDR4
•Firm grasp of constrained-random testing and coverage-driven verification
•Experience with formal analysis
•Practice using Python, Perl, Bash or other scripting languages
•Ability to work in a Linux environment
•Strong analysis and problem-solving skills
Security Requirement:
•The ability to obtain a US secret clearance is required which requires proof of US citizenship
•Active secret clearance is preferred
Contact: zbossi@judge.com
This job and many more are available through The Judge Group. Find us on the web at www.judge.com
