Technical Engineering Intern at Synopsys
Posted in Other 30+ days ago.
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Type: Full Time
Location: Hillsboro, Oregon
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything where devices are getting smarter, everything s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
Our verification solutions enable leading semiconductor and systems companies to cut months off their design schedules by helping them verify advanced silicon chips together with software, faster. Our high performance simulation products help engineers find design bugs faster and achieve timely coverage convergence to create high-quality designs. This internship position is with our Verification Group.
- Work closely with senior engineers to work with large semi-conductor designs to migrate them to utilize the latest Synopsys simulation software - Work on VIP, including protocol verification, deployment and debug in one or more key interfaces including PCIe, USB, JESD204, RFFE, Interlaken, I2C, I3C. Knowledge in DRAM Memory and other protocols is a strong plus.
- Generate test cases, exception, coverage and examples to demonstrate requirements and failures to the simulator development team.
- Verify that new releases of simulation software address existing and outstanding issues.
- Performance bench marking of simulation software against various representative semi-conductor designs.
- The end goal is to successfully help deploy and integrate the Verification IP into the customer's environment
Skill Requirements: - Very good understanding of the concept of logic simulation and verification
- Comfort and experience with Unix and Linux operating system and various scripting languages such as Python, PERL, TCL or similar
- Familiarity with Verilog, SystemVerilog, VHDL hardware description languages with strong understanding of design for verification methodologies is required (UVM)
- Excellent problem solving and ability to independently learn technical details and concepts.
- Must be currently enrolled in a Bachelors or Masters program pursuing Computer Science or Computer Engineering