NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020.
Business Unit Description
MCU/MPU Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, Ethernet, high-speed serial links, cores, caches, and interconnect.
Responsibilities include:
Collaborate with lead designer to review IP architecture specifications, features and programming model, microarchitecture and interface specifications, and identify areas of design that may present excess complexity in verification, or require special tools.
Plan IP verification, including providing resource and schedule assessments.
Design IP verification testbench (drivers, monitors, checkers, sequences) meeting requirements for quality and performance, using UVM, Verilog and System Verilog RTL, vendor and internal VIP.
Develop test plans, implement test cases, and complete verification execution to 100% coverage, and as per NXP standard quality and maturity standards.
Deliver portable stimulus and sequences to subsystem and SoC teams.
Propose and use alternate methods of verification, such as formal tools or C testcases, where appropriate to improve quality, reusability, and efficiency.
Track metrics during IP development, include test plan completion, code and functional coverage, defect tickets, and tracing of testcases versus requirements.
Collaborate with design team to provide expert support to subsystem, SoC, validation, and applications engineering teams.
Key challenges are:
Proving design meets all requirements and ensuring zero defects escape to silicon.
Meeting committed schedules without compromising quality
Cross-functional aspects:
Definition reviews with architecture teams and designers
Planning with designers, design manager, and project manager
Verification plan execution with local and global verification teams
Support for and feedback from local customers on IP, subsystem and SoC verification teams, emulation and silicon validation teams
Support for applications engineers and end-customers to replicate and root cause field failures, and verify workarounds.
Collaborate with local and global verification and tools development teams in developing improved methods of verification
Job Qualifications:
Minimum BSEE/BSCE/BSCS
Minimum 8 years of experience in IP or SoC design or verification
Expert knowledge of SystemVerilog UVM testbench development and stimulus generation required
Knowledge of LINUX-based code development required
Knowledge of Synopsys simulation tools strongly desired
Knowledge of PCI Express or serial Ethernet (SGMII, USXGMII, 10GBase-KR) strongly desired
Knowledge of functional safety, including ISO26262 a plus
Knowledge of CPU or cache architecture a plus
Expert knowledge of verification tool development a plus
Knowledge of formal verification techniques a plus
Knowledge of C coding a plus
Knowledge of scripting, such as Perl or Python, a plus
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
